Information: Building the design 'SRAM_8R8W' instantiated from design 'InstructionBuffer' with
	the parameters "16,4,126". (HDL-193)
Warning: Cannot find the design 'SRAM_8R8W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_PAYLOAD' instantiated from design 'IssueQueue' with
	the parameters "32,5,130". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_PAYLOAD' in the library 'WORK'. (LBR-1)
Information: Building the design 'CAM_4R4W' instantiated from design 'IssueQueue' with
	the parameters "32,5,7". (HDL-193)
Warning: Cannot find the design 'CAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_8R4W_PIPE' instantiated from design 'RegRead' with
	the parameters "96,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_PIPE' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,55". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,8". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,1". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_AMT' instantiated from design 'ArchMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_AMT' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,17". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,35". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_2R1W_HY' instantiated from design 'BranchPrediction' with
	the parameters "32768,15,2,4,2". (HDL-193)
Warning: Cannot find the design 'SRAM_2R1W_HY' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_FREELIST' instantiated from design 'SpecFreeList' with
	the parameters "62,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_FREELIST' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_8R4W_RMT' instantiated from design 'RenameMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_RMT' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'SRAM_8R8W' in 'InstructionBuffer'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_PAYLOAD' in 'IssueQueue'. (LINK-5)
Warning: Unable to resolve reference 'CAM_4R4W' in 'IssueQueue'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_8R4W_PIPE' in 'RegRead'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W' in 'ActiveList'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_AMT' in 'ArchMapTable'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_1R1W' in 'BTB'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_2R1W_HY' in 'BranchPrediction'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_FREELIST' in 'SpecFreeList'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_8R4W_RMT' in 'RenameMapTable'. (LINK-5)

Information: There are 10874 potential problems in your design. Please run 'check_design' for more information. (LINT-99)



  Beginning Pass 1 Mapping
  ------------------------
  Processing 'ArchMapTable'
  Processing 'ActiveList'
  Processing 'CommitStore'
  Processing 'CommitLoad'
  Processing 'DispatchedStore'
  Processing 'DispatchedLoad'
  Processing 'L1DataCache'
  Processing 'LSU'
Information: The register 'ldqAddr1_reg[31][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[31][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[30][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[30][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[29][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[29][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[28][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[28][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[27][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[27][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[26][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[26][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[25][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[25][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[24][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[24][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[23][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[23][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[22][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[22][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[21][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[21][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[20][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[20][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[19][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[19][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[18][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[18][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[17][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[17][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[16][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[16][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[15][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[15][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[14][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[14][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[13][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[13][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[12][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[12][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[11][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[11][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[10][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[10][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[9][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[9][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[8][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[8][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[7][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[7][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[6][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[6][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[5][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[5][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[4][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[4][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[3][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[3][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[2][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[2][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[1][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[1][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[0][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'ldqAddr1_reg[0][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[31][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[31][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[30][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[30][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[29][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[29][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[28][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[28][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[27][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[27][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[26][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[26][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[25][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[25][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[24][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[24][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[23][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[23][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[22][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[22][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[21][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[21][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[20][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[20][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[19][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[19][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[18][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[18][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[17][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[17][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[16][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[16][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[9][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[9][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[8][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[8][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[15][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[15][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[14][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[14][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[13][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[13][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[12][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[12][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[11][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[11][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[10][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[10][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[7][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[7][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[6][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[6][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[5][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[5][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[4][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[4][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[3][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[3][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[2][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[2][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[1][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[1][31]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[0][30]' is a constant and will be removed. (OPT-1206)
Information: The register 'stqAddr1_reg[0][31]' is a constant and will be removed. (OPT-1206)
  Processing 'AgenLsu'
  Processing 'WriteBack'
Information: The register 'lsuPacket0_reg[59]' will be removed. (OPT-1207)
Information: The register 'lsuPacket0_reg[61]' will be removed. (OPT-1207)
Information: The register 'lsuPacket0_reg[60]' will be removed. (OPT-1207)
Information: The register 'lsuPacket0_reg[62]' will be removed. (OPT-1207)
Information: The register 'exePacket2_reg[103]' will be removed. (OPT-1207)
Information: The register 'exePacket2_reg[105]' will be removed. (OPT-1207)
Information: The register 'exePacket2_reg[104]' will be removed. (OPT-1207)
Information: The register 'exePacket2_reg[106]' will be removed. (OPT-1207)
Information: The register 'exePacket1_reg[103]' will be removed. (OPT-1207)
Information: The register 'exePacket1_reg[105]' will be removed. (OPT-1207)
Information: The register 'exePacket1_reg[104]' will be removed. (OPT-1207)
Information: The register 'exePacket1_reg[106]' will be removed. (OPT-1207)
Information: The register 'exePacket0_reg[103]' will be removed. (OPT-1207)
Information: The register 'exePacket0_reg[105]' will be removed. (OPT-1207)
Information: The register 'exePacket0_reg[104]' will be removed. (OPT-1207)
Information: The register 'exePacket0_reg[106]' will be removed. (OPT-1207)
  Processing 'ForwardCheck_0'
  Processing 'ForwardCheck_1'
  Processing 'AGEN'
  Processing 'FU3'
  Processing 'Ctrl_ALU'
  Processing 'FU2'
  Processing 'Complex_ALU'
  Processing 'FU1'
  Processing 'Simple_ALU'
  Processing 'FU0'
  Processing 'Execute'
  Processing 'RegReadExecute'
  Processing 'RegRead'
  Processing 'IssueqRegRead'
  Processing 'RSR2'
Information: The register 'branchMask1_reg[4]' will be removed. (OPT-1207)
Information: The register 'branchMask1_reg[5]' will be removed. (OPT-1207)
Information: The register 'branchMask1_reg[6]' will be removed. (OPT-1207)
Information: The register 'branchMask0_reg[4]' will be removed. (OPT-1207)
Information: The register 'branchMask0_reg[5]' will be removed. (OPT-1207)
Information: The register 'branchMask0_reg[6]' will be removed. (OPT-1207)
Information: The register 'branchMask2_reg[4]' will be removed. (OPT-1207)
Information: The register 'branchMask2_reg[5]' will be removed. (OPT-1207)
Information: The register 'branchMask2_reg[6]' will be removed. (OPT-1207)
  Processing 'PriorityEncoder_ENCODER_WIDTH4_0'
  Processing 'selectBlock_4_0'
  Processing 'PriorityEncoder_ENCODER_WIDTH8_0'
  Processing 'selectBlock_8_0'
  Processing 'PriorityEncoder_ENCODER_WIDTH8_1'
  Processing 'selectBlock_8_1'
  Processing 'Encoder_ENCODER_WIDTH32_ENCODER_WIDTH_LOG5_0'
  Processing 'Select_0'
  Processing 'PriorityEncoder_ENCODER_WIDTH4_1'
  Processing 'selectBlock_4_1'
  Processing 'Select_1'
  Processing 'selectFromBlock_0_0'
  Processing 'FreeIssueq'
  Processing 'IssueQFreeList'
  Processing 'IssueQueue'
  Processing 'Dispatch'
  Processing 'RenameDispatch'
  Processing 'RenameMapTable'
Warning: Cell 'U59/U1' (*GEN*53655) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U60/U1' (*GEN*53654) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U61/U1' (*GEN*53653) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U62/U1' (*GEN*53652) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
  Processing 'SpecFreeList'
Warning: Cell 'U10/U1' (*GEN*53575) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U11/U1' (*GEN*53574) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U12/U1' (*GEN*53573) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U56/U1' (*GEN*53571) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U57/U1' (*GEN*53570) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U58/U1' (*GEN*53569) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U59/U1' (*GEN*53568) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U60/U1' (*GEN*53567) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U61/U1' (*GEN*53566) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U62/U1' (*GEN*53565) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U63/U1' (*GEN*53564) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'C507' (GTECH_OR5) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
  Processing 'Rename'
  Processing 'InstBufRename'
  Processing 'InstructionBuffer'
  Processing 'Decode_PISA_0'
  Processing 'Decode_PISA_1'
  Processing 'Decode'
  Processing 'Fetch2Decode'
  Processing 'PreDecode_PISA_0'
  Processing 'PreDecode_PISA_1'
  Processing 'CtrlQueue'
  Processing 'FetchStage2'
  Processing 'Fetch1Fetch2'
  Processing 'L1ICache'
  Processing 'RAS'
  Processing 'BranchPrediction'
Warning: Cell 'U4/U1' (*GEN*49673) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U6/U1' (*GEN*49671) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
  Processing 'BTB'
Warning: Cell 'U4/U1' (*GEN*49442) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U5/U1' (*GEN*49441) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U6/U1' (*GEN*49440) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
Warning: Cell 'U7/U1' (*GEN*49439) cannot be exactly translated 1 for 1 into target library.  Ignoring set_compile_directives. (TRANS-9)
  Processing 'FetchStage1'
  Processing 'Interface'
  Processing 'FABSCALAR'
Information: Building the design 'SRAM_8R8W' instantiated from design 'InstructionBuffer' with
	the parameters "16,4,126". (HDL-193)
Warning: Cannot find the design 'SRAM_8R8W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_PAYLOAD' instantiated from design 'IssueQueue' with
	the parameters "32,5,130". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_PAYLOAD' in the library 'WORK'. (LBR-1)
Information: Building the design 'CAM_4R4W' instantiated from design 'IssueQueue' with
	the parameters "32,5,7". (HDL-193)
Warning: Cannot find the design 'CAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_8R4W_PIPE' instantiated from design 'RegRead' with
	the parameters "96,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_PIPE' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,55". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,8". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,32". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W' instantiated from design 'ActiveList' with
	the parameters "128,7,1". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_AMT' instantiated from design 'ArchMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_AMT' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,17". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_1R1W' instantiated from design 'BTB' with
	the parameters "1024,10,35". (HDL-193)
Warning: Cannot find the design 'SRAM_1R1W' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_2R1W_HY' instantiated from design 'BranchPrediction' with
	the parameters "32768,15,2,4,2". (HDL-193)
Warning: Cannot find the design 'SRAM_2R1W_HY' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_4R4W_FREELIST' instantiated from design 'SpecFreeList' with
	the parameters "62,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_4R4W_FREELIST' in the library 'WORK'. (LBR-1)
Information: Building the design 'SRAM_8R4W_RMT' instantiated from design 'RenameMapTable' with
	the parameters "34,6,7". (HDL-193)
Warning: Cannot find the design 'SRAM_8R4W_RMT' in the library 'WORK'. (LBR-1)
Warning: Unable to resolve reference 'SRAM_8R8W' in 'InstructionBuffer'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_PAYLOAD' in 'IssueQueue'. (LINK-5)
Warning: Unable to resolve reference 'CAM_4R4W' in 'IssueQueue'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_8R4W_PIPE' in 'RegRead'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W' in 'ActiveList'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_AMT' in 'ArchMapTable'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_1R1W' in 'BTB'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_2R1W_HY' in 'BranchPrediction'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_4R4W_FREELIST' in 'SpecFreeList'. (LINK-5)
Warning: Unable to resolve reference 'SRAM_8R4W_RMT' in 'RenameMapTable'. (LINK-5)

  Updating timing information
Information: Updating design information... (UID-85)

  Beginning Implementation Selection
  ----------------------------------
  Processing 'Decode_PISA_2_DW01_add_0'
  Processing 'Decode_PISA_2_DW01_inc_0'
  Processing 'Decode_PISA_3_DW01_add_0'
  Processing 'Decode_PISA_3_DW01_inc_0'
  Processing 'Decode_PISA_1_DW01_add_0'
  Processing 'Decode_PISA_1_DW01_inc_0'
  Processing 'PreDecode_PISA_2_DW01_add_0'
  Processing 'PreDecode_PISA_2_DW01_add_1'
  Processing 'PreDecode_PISA_3_DW01_add_0'
  Processing 'PreDecode_PISA_3_DW01_add_1'
  Processing 'PreDecode_PISA_1_DW01_add_0'
  Processing 'PreDecode_PISA_1_DW01_add_1'

  Beginning Mapping Optimizations  (Medium effort)
  -------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:05:48 1320419.1    110.03  261794.9   26132.0                          
    0:05:48 1320419.1    110.03  261794.9   26132.0                          
    0:05:50 1317229.4    110.03  249051.7   24857.9                          
    0:05:50 1310205.9    110.03  249036.5   23330.9                          
    0:05:54 1309492.4    110.03  225962.8    5937.5                          
    0:05:58 1311953.6    104.56  225497.0    3712.6                          
    0:06:00 1308424.3    104.56  157873.5    2669.3                          
    0:06:03 1309608.7     96.30  151122.9    2542.1                          
    0:06:06 1313892.4     96.30  148499.6    2253.3                          
    0:07:20 1504826.4     64.85  139196.3    1000.4                          
    0:07:20 1504826.4     64.85  139196.3    1000.4                          
    0:07:20 1504826.4     64.85  139196.3    1000.4                          
    0:07:21 1504826.4     64.85  139196.3    1000.4                          
    0:07:23 1504826.4     64.85  139196.3    1000.4                          
    0:07:59 1250411.3     43.25     775.7     108.4                          
    0:08:08 1248084.4     42.82     741.4     108.0                          
    0:08:20 1248106.5     42.82     732.8     108.0                          
    0:08:22 1248112.1     42.82     732.8     108.0                          
    0:08:28 1248130.3     42.06     726.7     108.0                          
    0:08:29 1248133.5     41.83     724.8     108.0                          
    0:08:30 1248148.3     41.83     724.8     108.0                          
    0:08:32 1248151.4     41.70     723.8     108.0                          
    0:08:33 1248167.0     40.90     718.3     108.0                          
    0:08:34 1237014.8     40.90     718.3     108.0                          
    0:08:35 1237014.8     40.90     718.3     108.0                          
    0:08:35 1237014.8     40.90     718.3     108.0                          
    0:08:35 1237014.8     40.90     718.3     108.0                          
    0:08:35 1237014.8     40.90     718.3     108.0                          



  Beginning Delay Optimization Phase
  ----------------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:08:36 1236773.9     40.90     718.3     108.0                          
    0:08:37 1236844.6     38.93     702.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:37 1236914.8     38.53     699.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:38 1237009.2     38.00     695.3     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:39 1237122.4     37.67     692.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:40 1237163.6     37.27     689.4     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:41 1237251.6     36.66     684.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:42 1237310.3     36.48     683.0     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:43 1237339.5     34.79     669.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:43 1237391.9     33.92     662.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:44 1237513.4     31.60     644.1     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:45 1237584.7     31.17     640.6     108.0 writebk/ldViolationPacket_reg[3]/D
    0:08:45 1237657.3     30.31     633.8     108.0 writebk/ldViolationPacket_reg[3]/D
    0:08:46 1237654.9     30.15     632.4     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:47 1237718.3     29.30     625.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:47 1237755.6     28.63     620.3     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:47 1237755.1     28.60     620.1     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:48 1237819.5     28.53     619.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:48 1237851.1     28.46     619.0     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:49 1237896.9     28.36     618.1     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:49 1237946.7     28.30     617.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:49 1238024.5     28.19     616.8     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:50 1238011.6     28.14     616.4     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:50 1238007.0     28.09     616.0     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:51 1238064.2     27.93     614.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:51 1238095.1     27.76     613.3     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:52 1238096.0     27.73     613.2     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:52 1238101.4     27.18     608.8     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:52 1238144.8     27.08     608.0     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:53 1238187.1     26.15     600.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:53 1238222.0     26.05     599.7     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:54 1238223.0     26.04     599.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:54 1238231.0     25.95     598.9     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:54 1238237.0     25.90     598.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:55 1238246.1     25.83     597.9     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:55 1238250.7     25.82     597.9     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:56 1238369.2     23.19     576.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:56 1238382.2     22.75     573.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:57 1238402.5     22.64     572.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:57 1238428.0     22.61     572.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:57 1238429.9     22.44     570.9     108.0 writebk/ldViolationPacket_reg[2]/D
    0:08:58 1238472.2     22.29     569.9     108.0 writebk/ldViolationPacket_reg[3]/D
    0:08:58 1238505.4     22.22     569.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:59 1238518.5     22.16     568.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:59 1238552.4     22.14     568.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:08:59 1238581.7     22.10     568.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:00 1238610.7     21.99     567.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:00 1238625.7     21.88     566.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:01 1238661.9     21.54     563.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:01 1238688.6     21.51     563.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:02 1238706.1     21.21     561.2     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:02 1238697.8     21.21     561.2     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:02 1238708.0     20.81     558.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:03 1238721.0     20.70     556.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:04 1238762.9     20.35     554.2     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:04 1238779.0     20.34     554.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:04 1238775.1     20.12     552.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:05 1238781.6     20.11     552.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:05 1238798.9     20.09     552.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:05 1238799.9     20.08     552.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:06 1238803.0     20.05     551.7     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:06 1238817.0     19.99     551.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:07 1238836.8     19.93     550.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:07 1238852.3     19.92     550.7     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:08 1238842.5     19.28     545.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:08 1238843.9     19.15     544.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:09 1238839.3     18.69     540.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:09 1238840.0     18.35     538.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:10 1238840.9     18.35     538.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:10 1238845.7     18.25     537.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:10 1238845.0     18.08     535.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:11 1238850.8     17.94     535.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:11 1238864.3     17.84     534.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:11 1238864.3     17.84     534.3     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:12 1238894.1     17.00     527.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:12 1238881.7     16.90     526.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:12 1238880.7     16.90     526.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:13 1238889.7     16.50     523.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:13 1238985.7     15.36     514.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:14 1239008.8     15.25     513.6     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:14 1239047.3     15.13     512.6     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:14 1239074.8     14.94     511.1     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:15 1239108.5     14.93     511.0     108.0 writebk/ldViolationPacket_reg[5]/D
    0:09:15 1239104.3     14.30     506.0     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:15 1239104.1     14.29     505.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:16 1239107.4     14.05     504.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:16 1239124.2     13.86     502.7     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:16 1239125.2     13.82     502.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:17 1239144.8     13.80     502.2     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:17 1239171.0     13.72     501.6     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:17 1239180.1     13.72     501.5     108.0 writebk/ldViolationPacket_reg[7]/D
    0:09:18 1239209.5     13.69     501.3     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:18 1239226.0     13.62     500.7     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:19 1239259.2     13.49     499.6     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:19 1239265.4     13.47     499.5     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:19 1239258.3     13.43     499.2     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:20 1239276.5     13.37     498.7     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:20 1239285.5     12.69     493.2     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:20 1239310.8     12.50     491.7     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:21 1239324.2     12.01     487.8     108.0 writebk/ldViolationPacket_reg[3]/D
    0:09:21 1239338.0     12.00     487.7     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:21 1239346.8     11.97     487.5     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:22 1239362.2     11.95     487.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:22 1239362.2     11.95     487.4     108.0 writebk/ldViolationPacket_reg[2]/D
    0:09:22 1239378.5     11.89     486.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:22 1239376.6     11.89     486.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:23 1239376.6     11.88     486.7     108.0 writebk/ldViolationPacket_reg[6]/D
    0:09:23 1239393.4     11.85     486.5     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:23 1239393.4     11.83     486.4     108.0 writebk/ldViolationPacket_reg[7]/D
    0:09:23 1239425.7     11.78     486.1     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:23 1239425.7     11.77     486.0     108.0 writebk/ldViolationPacket_reg[5]/D
    0:09:24 1239428.5     11.44     483.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:24 1239442.0     11.44     483.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:24 1239455.5     11.40     483.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:25 1239473.7     11.36     482.7     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:25 1239501.4     11.34     482.5     108.0 writebk/ldViolationPacket_reg[4]/D
    0:09:25 1239518.0     11.33     482.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:26 1239611.5     11.21     481.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:26 1239688.8     11.17     465.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:27 1239633.7     11.08     464.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:27 1239634.7     11.06     464.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:27 1239652.6     10.99     463.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:28 1239657.0     10.68     460.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:28 1239677.3     10.58     448.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:29 1239681.0     10.57     448.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:29 1239683.9     10.53     447.6     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:29 1239697.0     10.49     447.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:29 1239701.6     10.49     447.3     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:30 1239756.1     10.29     440.5     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:30 1239802.4      9.54     401.7     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:31 1239822.2      9.51     401.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:31 1239826.4      9.21     399.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:32 1239826.4      9.13     398.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:32 1240015.3      9.12     397.0     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:32 1240019.9      9.12     396.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:33 1240053.9      9.12     396.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:33 1240053.9      9.04     365.2     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:34 1240035.2      8.95     364.4     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:34 1240058.1      8.89     363.9     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:35 1240159.6      8.75     358.8     108.0 writebk/ldViolationPacket_reg[1]/D
    0:09:36 1240290.3      8.19     354.8     127.2 writebk/ldViolationPacket_reg[1]/D
    0:09:36 1240432.6      8.04     343.8     151.9 writebk/ldViolationPacket_reg[1]/D
    0:09:36 1240441.9      8.03     343.7     151.9 writebk/ldViolationPacket_reg[1]/D
    0:09:37 1240438.8      8.01     343.4     151.9 writebk/ldViolationPacket_reg[1]/D
    0:09:37 1240459.9      7.94     340.6     151.9 writebk/ldViolationPacket_reg[1]/D
    0:09:38 1240535.3      7.40     310.7     171.0 writebk/ldViolationPacket_reg[4]/D
    0:09:39 1240567.2      7.27     309.8     171.0 writebk/ldViolationPacket_reg[1]/D
    0:09:39 1240617.0      7.20     308.3     171.0 writebk/ldViolationPacket_reg[1]/D
    0:09:39 1240614.3      7.20     308.3     171.0 writebk/ldViolationPacket_reg[4]/D
    0:09:40 1240617.9      7.20     308.2     171.0 writebk/ldViolationPacket_reg[4]/D
    0:09:40 1240661.1      7.06     304.8     171.0 writebk/ldViolationPacket_reg[4]/D
    0:09:41 1240663.6      6.73     263.2     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:42 1240676.5      6.57     262.0     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:42 1240711.0      6.55     261.8     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:42 1240709.2      6.50     262.0     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:43 1240707.7      6.42     261.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:43 1240693.8      6.29     260.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:43 1240706.2      6.26     260.0     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:44 1240762.5      6.22     259.7     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:44 1240780.4      6.19     259.4     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:44 1240819.0      6.11     258.8     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:45 1240819.9      6.10     258.7     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:45 1240829.2      6.06     258.4     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:45 1240854.5      5.98     257.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:46 1240897.8      5.92     230.2     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:46 1240905.8      5.88     229.8     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:46 1240905.8      5.85     229.5     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:47 1240916.9      5.84     229.4     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:47 1240971.2      5.82     229.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:47 1240938.6      5.79     229.1     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:47 1240936.7      5.76     228.8     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:48 1240943.0      5.75     228.7     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:48 1240947.6      5.75     228.7     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:48 1240964.7      5.67     226.7     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:49 1240948.1      5.64     226.5     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:49 1240943.0      5.61     226.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:50 1241022.0      5.41     224.3     151.8 writebk/ldViolationPacket_reg[4]/D
    0:09:50 1241002.4      5.34     221.1     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:51 1241046.1      5.27     220.6     152.0 writebk/ldViolationPacket_reg[1]/D
    0:09:51 1241069.9      5.23     220.3     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:51 1241077.1      5.18     219.9     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:52 1241071.6      5.17     219.9     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:52 1241072.0      5.16     219.7     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:52 1241076.6      5.16     219.7     152.0 writebk/ldViolationPacket_reg[1]/D
    0:09:52 1241076.6      5.14     219.5     152.0 writebk/ldViolationPacket_reg[1]/D
    0:09:53 1241119.4      5.08     214.8     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:53 1241126.9      5.01     214.2     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:53 1241142.8      5.01     214.2     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:54 1241139.1      5.00     214.1     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:54 1241172.9      4.95     212.1     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:54 1241218.7      4.95     212.1     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:55 1241259.4      4.80     202.6     152.0 instBuf/instCount_reg[4]/D
    0:09:56 1241393.3      4.62     188.0     152.0 writebk/ldViolationPacket_reg[3]/D
    0:09:56 1241399.8      4.62     188.0     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:57 1241405.4      4.47     186.8     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:57 1241422.9      4.43     186.5     152.0 writebk/ldViolationPacket_reg[3]/D
    0:09:58 1241417.3      4.42     186.3     152.0 writebk/ldViolationPacket_reg[1]/D
    0:09:58 1241442.7      4.39     181.0     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:58 1241462.1      4.37     180.8     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:59 1241445.5      4.23     177.5     152.0 writebk/ldViolationPacket_reg[4]/D
    0:09:59 1241475.4      3.93     161.4     152.0 writebk/ldViolationPacket_reg[1]/D
    0:10:00 1241486.4      3.92     161.3     152.0 instBuf/instCount_reg[4]/D
    0:10:00 1241539.6      3.91     159.4     152.0 instBuf/instCount_reg[4]/D
    0:10:00 1241551.1      3.87     159.1     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:01 1241596.5      3.79     158.6     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:01 1241620.3      3.76     158.3     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:02 1241635.9      3.73     157.0     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:02 1241702.2      3.71     155.9     152.0 lsu/precedingSTvalid_reg[2]/D
    0:10:03 1241724.4      3.69     147.4     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:03 1241742.8      3.68     147.3     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:03 1241736.4      3.68     147.3     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:03 1241765.0      3.66     147.2     152.0 writebk/ldViolationPacket_reg[2]/D
    0:10:04 1241788.9      3.63     146.9     152.0 writebk/ldViolationPacket_reg[3]/D
    0:10:04 1241789.1      3.63     146.9     152.0 writebk/ldViolationPacket_reg[4]/D
    0:10:04 1241780.6      3.61     146.8     152.0 writebk/ldViolationPacket_reg[4]/D
    0:10:05 1241792.7      3.55     146.1     152.0 writebk/ldViolationPacket_reg[4]/D
    0:10:06 1241884.7      3.48     145.3     152.0 writebk/ldViolationPacket_reg[4]/D
    0:10:07 1242025.6      3.42     142.9     157.6 lsu/precedingSTvalid_reg[2]/D
    0:10:07 1242039.1      3.40     142.7     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:08 1242050.7      3.39     141.9     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:08 1242065.2      3.39     141.9     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:08 1242114.3      3.37     141.8     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:09 1242227.7      3.36     113.7     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:09 1242235.3      3.36     113.6     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:10 1242224.2      3.36     113.6     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:10 1242261.4      3.34     113.5     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:10 1242262.3      3.26     112.9     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:11 1242294.5      3.24     112.8     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:11 1242336.5      3.23     112.7     157.6 instBuf/instCount_reg[4]/D
    0:10:11 1242336.5      3.23     112.7     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:12 1242341.9      3.22     112.6     157.6 writebk/ldViolationPacket_reg[4]/D
    0:10:12 1242417.8      3.20     110.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:12 1242435.5      3.20     110.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:13 1242493.0      2.97     108.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:13 1242505.8      2.91     108.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:14 1242545.7      2.80     107.6     300.7 instBuf/instCount_reg[4]/D
    0:10:14 1242534.1      2.76     107.1     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:15 1242638.5      2.76     106.2     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:15 1242650.6      2.75     106.1     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:16 1242686.5      2.71     105.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:16 1242650.9      2.70     105.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:17 1242663.6      2.65     105.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:17 1242665.6      2.58     103.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:18 1242695.8      2.49     103.0     300.7 lsu/precedingSTvalid_reg[2]/D
    0:10:19 1242763.0      2.40      95.9     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:19 1242798.4      2.39      95.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:20 1242816.9      2.34      95.2     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:20 1242841.4      2.33      95.0     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:21 1242912.3      2.31      94.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:21 1242908.6      2.30      94.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:22 1242926.3      2.29      94.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:22 1242909.2      2.25      93.2     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:22 1242946.9      2.25      91.4     300.7 lsu/precedingSTvalid_reg[2]/D
    0:10:23 1242987.4      2.24      91.3     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:23 1242994.6      2.23      91.3     300.7 instBuf/instCount_reg[4]/D
    0:10:24 1242999.2      2.23      91.3     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:24 1243009.1      2.23      90.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:25 1243090.6      2.16      87.5     300.7 instBuf/instCount_reg[4]/D
    0:10:25 1243110.9      2.09      80.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:25 1243106.3      2.09      80.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:26 1243122.5      2.08      80.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:26 1243133.9      2.04      80.1     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:27 1243196.4      2.00      79.6     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:28 1243204.7      1.99      79.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:28 1243250.0      1.99      79.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:28 1243279.1      1.98      79.2     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:29 1243295.9      1.93      78.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:29 1243307.5      1.91      78.2     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:30 1243572.0      1.90      73.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:30 1243572.0      1.90      73.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:31 1243603.2      1.90      73.3     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:31 1243601.5      1.88      73.1     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:31 1243601.7      1.88      73.1     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:32 1243682.0      1.86      72.9     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:32 1243682.0      1.86      72.9     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:32 1243691.2      1.86      72.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:33 1243667.0      1.85      72.6     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:33 1243667.9      1.84      72.6     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:33 1243658.4      1.83      72.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:34 1243663.9      1.82      72.3     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:34 1243692.6      1.78      71.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:35 1243691.1      1.78      71.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:35 1243682.5      1.77      71.8     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:35 1243674.2      1.77      71.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:36 1243674.2      1.76      71.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:36 1243679.6      1.76      71.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:36 1243734.1      1.76      66.7     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:37 1243799.6      1.74      66.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:37 1243799.6      1.74      66.5     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:38 1243806.2      1.73      66.4     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:38 1243838.6      1.73      66.4     300.7 instBuf/instCount_reg[4]/D
    0:10:39 1243854.2      1.72      66.3     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:39 1243874.4      1.71      66.0     300.7 writebk/ldViolationPacket_reg[4]/D
    0:10:39 1243876.3      1.70      66.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:39 1243879.1      1.67      65.7     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:40 1243907.8      1.65      65.3     300.8 instBuf/instCount_reg[4]/D
    0:10:40 1243964.3      1.62      65.1     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:41 1243988.5      1.58      62.3     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:41 1244027.5      1.57      62.1     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:42 1244037.6      1.57      62.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:42 1244040.4      1.57      62.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:43 1244046.3      1.57      62.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:43 1244028.8      1.56      62.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:43 1244028.8      1.56      62.0     300.8 writebk/ldViolationPacket_reg[4]/D
    0:10:44 1244043.9      1.54      61.7     300.9 writebk/ldViolationPacket_reg[4]/D
    0:10:44 1244048.8      1.54      61.7     300.9 writebk/ldViolationPacket_reg[4]/D
    0:10:45 1244073.6      1.53      60.6     300.9 writebk/ldViolationPacket_reg[4]/D
    0:10:45 1244059.9      1.53      60.5     300.9 writebk/ldViolationPacket_reg[4]/D
    0:10:45 1244071.0      1.52      59.5     300.9 instBuf/instCount_reg[4]/D
    0:10:46 1244054.6      1.49      56.7     301.0 writebk/ldViolationPacket_reg[4]/D
    0:10:46 1244042.3      1.48      56.7     301.0 writebk/ldViolationPacket_reg[4]/D
    0:10:46 1244043.3      1.48      56.7     301.0 writebk/ldViolationPacket_reg[4]/D
    0:10:47 1243872.5      1.44      51.2     281.9 instBuf/instCount_reg[4]/D
    0:10:47 1243875.2      1.44      51.2     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:47 1243887.5      1.42      51.0     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:48 1243885.1      1.40      49.5     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:48 1243979.8      1.34      15.9     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:49 1244009.4      1.31      15.7     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:49 1244012.4      1.28      15.4     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:49 1244024.4      1.28      15.4     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:49 1244029.9      1.28      15.4     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:50 1244045.8      1.27      15.4     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:50 1244045.8      1.27      15.4     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:50 1244068.2      1.26      15.3     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:51 1244072.7      1.25      15.2     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:51 1244110.8      1.21      15.0     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:52 1244099.6      1.18      14.8     281.9 writebk/ldViolationPacket_reg[4]/D
    0:10:52 1244126.2      1.09      14.1     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:53 1244131.9      1.06      13.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:53 1244155.3      1.04      13.8     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:53 1244175.1      1.03      13.7     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:53 1244158.1      1.00      13.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:54 1244179.5      0.96      13.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:54 1244178.7      0.93      13.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:54 1244177.8      0.93      13.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:55 1244179.6      0.91      12.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:55 1244173.2      0.91      12.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:55 1244175.2      0.90      12.8     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:56 1244162.9      0.87      12.6     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:56 1244187.5      0.86      12.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:56 1244180.7      0.83      12.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:57 1244187.2      0.83      12.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:57 1244237.4      0.74      11.7     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:57 1244266.1      0.73      11.6     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:57 1244257.9      0.71      11.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:58 1244254.6      0.69      11.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:58 1244285.7      0.67      11.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:58 1244300.3      0.65      11.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:59 1244292.1      0.64      11.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:59 1244282.3      0.61      10.8     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:59 1244314.9      0.60      10.7     282.0 writebk/ldViolationPacket_reg[4]/D
    0:10:59 1244318.2      0.58      10.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:00 1244335.0      0.57      10.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:00 1244344.2      0.56      10.4     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:00 1244394.0      0.53      10.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:01 1244413.5      0.52      10.1     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:01 1244423.8      0.52      10.1     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:01 1244436.3      0.51      10.1     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:02 1244457.4      0.48       9.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:02 1244467.9      0.31       8.7     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:03 1244484.6      0.30       8.6     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:03 1244532.5      0.29       7.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:03 1244552.4      0.27       6.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:04 1244547.2      0.25       6.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:04 1244578.3      0.19       4.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:04 1244608.6      0.15       3.6     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:05 1244700.3      0.15       3.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:05 1244695.7      0.14       3.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:05 1244692.1      0.14       3.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:05 1244702.5      0.13       1.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:05 1244648.2      0.13       1.5     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:06 1244684.4      0.11       1.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:06 1244699.1      0.11       1.3     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:07 1244684.5      0.09       1.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:07 1244684.5      0.09       1.2     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:07 1244707.2      0.08       1.1     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:07 1244721.9      0.06       1.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:08 1244706.2      0.05       0.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:08 1244714.9      0.04       0.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:08 1244714.9      0.04       0.9     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:08 1244725.3      0.04       0.8     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:09 1244745.6      0.00       0.0     282.0 writebk/ldViolationPacket_reg[4]/D
    0:11:09 1244745.6      0.00       0.0     282.0                          
    0:11:13 1244373.9      0.00       0.0     282.0                          


  Beginning Design Rule Fixing  (max_transition)  (max_capacitance)
  ----------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:11:13 1244373.9      0.00       0.0     282.0                          
    0:11:14 1244241.4      0.00       0.0       0.0                          


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

   ELAPSED            WORST NEG TOTAL NEG  DESIGN                            
    TIME      AREA      SLACK     SLACK   RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:11:14 1244241.4      0.00       0.0       0.0                          
    0:11:15 1244241.4      0.00       0.0       0.0                          
    0:11:37 1239299.4      0.01       0.0       0.0                          
    0:11:41 1237803.5      0.12       2.5       0.0                          
    0:11:44 1237147.5      0.12       2.5       0.0                          
    0:11:45 1236687.7      0.12       2.5       0.0                          
    0:11:46 1236470.7      0.12       2.5       0.0                          
    0:11:46 1236300.4      0.12       2.5       0.0                          
    0:11:47 1236181.5      0.12       2.5       0.0                          
    0:11:47 1236055.6      0.12       2.5       0.0                          
    0:11:47 1235960.7      0.12       2.5       0.0                          
    0:11:48 1235877.1      0.12       2.5       0.0                          
    0:11:48 1235877.1      0.12       2.5       0.0                          
    0:11:49 1235893.4      0.00       0.0       0.0 lsu/precedingSTvalid_reg[10]/D
    0:11:51 1235892.1      0.00       0.0       0.0                          
    0:11:53 1233702.4      0.04       0.3       0.0                          
    0:11:53 1233559.5      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:54 1233554.9      0.03       0.2       0.0                          
    0:11:56 1233583.9      0.00       0.0       0.0                          
    0:11:57 1233143.4      0.00       0.0       0.0                          
    0:11:57 1233071.5      0.00       0.0       0.0                          
    0:11:58 1232825.2      0.00       0.0       0.0                          
    0:11:59 1232488.6      0.00       0.0       0.0                          
    0:12:00 1232282.4      0.00       0.0       0.0                          
    0:12:01 1232241.5      0.00       0.0       0.0                          
    0:12:02 1232068.5      0.00       0.0       0.0                          
    0:12:02 1231933.2      0.00       0.0       0.0                          
    0:12:03 1231776.0      0.00       0.0       0.0                          
    0:12:04 1231421.3      0.00       0.0       0.0                          
    0:12:05 1231324.5      0.00       0.0       0.0                          
    0:12:07 1231203.7      0.00       0.0       0.0                          
    0:12:07 1231032.5      0.00       0.0       0.0                          
    0:12:09 1230899.6      0.00       0.0       0.0                          
    0:12:10 1230761.3      0.00       0.0       0.0                          
    0:12:11 1230354.8      0.00       0.0       0.0                          
    0:12:12 1230022.3      0.00       0.0       0.0                          
    0:12:13 1229903.7      0.00       0.0       0.0                          
    0:12:14 1229747.7      0.00       0.0       0.0                          
    0:12:14 1229641.0      0.00       0.0       0.0                          
    0:12:15 1229496.3      0.00       0.0       0.0                          
    0:12:16 1229249.5      0.00       0.0       0.0                          
    0:12:17 1228940.6      0.00       0.0       0.0                          
    0:12:18 1228701.8      0.00       0.0       0.0                          
    0:12:20 1228447.1      0.00       0.0       0.0                          
    0:12:21 1228184.1      0.00       0.0       0.0                          
    0:12:23 1227843.5      0.00       0.0       0.0                          
    0:12:23 1227528.9      0.00       0.0       0.0                          
    0:12:24 1227194.6      0.00       0.0       0.0                          
    0:12:25 1226811.3      0.00       0.0       0.0                          
    0:12:26 1226586.7      0.00       0.0       0.0                          
    0:12:27 1226416.3      0.00       0.0       0.0                          
    0:12:28 1226202.8      0.00       0.0       0.0                          
    0:12:28 1226160.3      0.00       0.0       0.0                          
    0:12:29 1226121.5      0.00       0.0       0.0                          
    0:12:29 1225889.4      0.00       0.0       0.0                          
    0:12:30 1225603.3      0.00       0.0       0.0                          
    0:12:31 1225302.5      0.00       0.0       0.0                          
    0:12:33 1225070.8      0.00       0.0       0.0                          
    0:12:34 1224732.9      0.00       0.0       0.0                          
    0:12:36 1224611.9      0.00       0.0       0.0                          
    0:12:39 1224580.1      0.00       0.0       0.0                          
    0:12:39 1224579.0      0.00       0.0       0.0                          
    0:12:40 1224574.0      0.00       0.0       0.0                          
    0:12:42 1224564.4      0.00       0.0       0.0                          
    0:12:43 1224560.0      0.00       0.0       0.0                          
    0:12:46 1224546.4      0.00       0.0       0.0                          
    0:12:51 1224531.1      0.00       0.0       0.0                          
    0:12:56 1224530.3      0.00       0.0       0.0                          
    0:12:58 1224524.2      0.00       0.0       0.0                          
    0:13:00 1224524.2      0.00       0.0       0.0                          
    0:13:01 1224431.1      0.02       0.1       0.0                          
    0:13:01 1224426.5      0.02       0.1       0.0                          
    0:13:01 1224426.5      0.02       0.1       0.0                          
    0:13:01 1224426.5      0.02       0.1       0.0                          
    0:13:02 1224426.5      0.02       0.1       0.0                          
    0:13:02 1224426.5      0.02       0.1       0.0                          
    0:13:02 1224426.5      0.02       0.1       0.0                          
    0:13:05 1228444.0      0.00       0.0       0.0                          
Loading db file '/net/plato.ee.virginia.edu/users/wz6pc/synopsys/syn_tut/dc/ref/models/saed90nm_typ_ht.db'

  Optimization Complete
  ---------------------
Warning: Design 'FABSCALAR' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
     Net 'issueq/select1/net39619': 11230 load(s), 1 driver(s), 22 inout(s)
1
